MPC106 데이터 시트보기 (PDF) - Motorola => Freescale

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MPC106

PCI Bridge/Memory Controller

Motorola => Freescale 

Electrical and Thermal Characteristics

Table 8. Output AC Timing Specifications

Num

Characteristic

66 MHz

Min

Max

83.3 MHz

Min

Max

Notes

12 SYSCLK to output driven (output

enable time)

2.0

—

2.0

—

1

13a SYSCLK to output valid for TS and

—

7.0

—

6.0

2, 3, 4

ARTRY

13b SYSCLK to output valid for all non-PCI

—

7.0

—

6.0

2, 3, 5

signals except TS, ARTRY, RAS[0–7],

CAS[0–7], and DWE[0-2]

14a SYSCLK to output valid (for RAS[0–7]

—

7.0

—

6.0

2, 3

and CAS[0–7])

14b SYSCLK to output valid for PCI signals

—

11.0

—

11.0

3, 6

15a SYSCLK to output invalid for all

non-PCI signals (output hold)

1.0

—

1.0

—

7, 10

15b SYSCLK to output invalid for PCI

signals (output hold)

1.0

—

1.0

—

7

18 SYSCLK to ARTRY high impedance

—

8.0

—

8.0

1

before precharge (output hold)

19 SYSCLK to ARTRY precharge enable

(0.4 *

—

(0.4 x

—

8, 1

tsysclk) + 2.0

tsysclk) + 2.0

21 SYSCLK to ARTRY high impedance

after precharge

—

(1.5 *

—

(1.5 x

8, 1

tsysclk) + 8.0

tsysclk) + 8.0

Notes:

1 These values are guaranteed by design and are not tested.

2 Output specifications are measured from 1.4 V on the rising edge of the appropriate clock to the TTL level (0.8

V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 5).

3 The maximum timing specification assumes CL = 50 pF.

4 The shared outputs TS and ARTRY require pull-up resistors to hold them negated when there is no bus master

driving them.

5 When the 106 is configured for asynchronous L2 cache SRAMs, the DWE[0–2] signals have a maximum

SYSCLK to output valid time of (0.5 x tPROC) + 8.0 ns (where tPROC is the 60x bus clock cycle time).

6 PCI 3.3 V signaling environment signals are measured from 1.65 V (Vdd ÷ 2) on the rising edge of SYSCLK to

VOH = 3.0 V or VOL = 0.3 V.

7 The minimum timing specification assumes CL = 0 pF.

8 tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tsysclk the

numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in

nanoseconds) of the parameter in question.

9 PCI devices which require more than the PCI-specified hold time of Th = 0ns or systems where clock skew

approaches the PCI-specified allowance of 2ns may not work with the MPC106. For workarounds, see Motorola

application note Designing PCI 2.1-Compliant MPC106 Systems (order number AN1727/D).

MPC106 PCI Bridge/Memory Controller Hardware Specifications

11

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