SC667201MMG2 데이터 시트보기 (PDF) - Freescale Semiconductor

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SC667201MMG2

Qorivva MPC5642A Microcontroller Data Sheet

Freescale Semiconductor 

1 Introduction

Introduction

1.1 Document overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5642A series of

microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical

characteristics. For functional characteristics, refer to the device reference manual.

1.2 Description

This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive

transmission control applications.

It is compatible with devices in Freescale’s MPC5600 family and offers performance and capabilities beyond the MPC5632M

devices.

The microcontroller’s e200z4 host processor core is built on the Power Architecture® technology and designed specifically for

embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal

processing (DSP).

The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM

and a 2 MB internal flash memory.

For development, the device includes a calibration bus that is accessible only when using the Freescale VertiCal Calibration

System.

1.3 Device feature summary

Table 1 summarizes the MPC5642A features and compares them to those of the MPC5644A.

Table 1. MPC5642A device feature summary

Feature

MPC5642A

MPC5644A

Process

Core

SIMD

VLE

Cache

Non-Maskable Interrupt (NMI)

MMU

MPU

Crossbar switch

Core performance

Windowing software watchdog

Core Nexus

SRAM

Flash

Flash fetch accelerator

90 nm

e200z4

Yes

Yes

8 KB instruction

NMI and Critical Interrupt

24-entry

16-entry

44

54

0–150 MHz

Yes

Class 3+

128 KB

192 KB

2 MB

4 MB

4  128-bit

4  256-bit

MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

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