1.2 Block diagram
System
integration
VReg
Oscillator
FMPLL 0
FMPLL 1
RTC/32Kosc
INTC
Debug
JTAG
Nexus 3+
eDMA
Crossbar switch masters
e200z4d
MMU
I-CACHE
GFX2D
DCULite
TCON / RSDS
VIU2
DCU3
Crossbar Switch
Memory Protection Unit
PIT
STM
SWT
Flash
memory
2 MB
EEE
SRAM
64 KB
BAM
Crossbar switch slaves
Communication I/O system
Graphics
SRAM
1 MB
PBRIDGE
QuadSPI
RLE decoder
DRAM interface
SSD
ADC
BAM
eDMA
DCU3
DCULite
DSPI
eMIOS
FlexCAN
FMPLL
GFX2D
INTC
JTAG
MMU
QuadSPI
– Analog-to-Digital Converter
– Boot Assist Module
– Enhanced Direct Memory Access Controller
– Display Control Unit
– Display Control Unit Lite
– Serial Peripherals Interface
– Enhanced Modular Input/Output System
– Controller Area Network Controller
– Frequency-Modulated Phase-Locked Loop
– OpenVG Graphics Accelerator
– Interrupt Controller
– Joint Test Action Group interface
– Memory Management Unit
– Quad IO serial flash interface
PBRIDGE – Peripheral Bridge
PIT
– Periodic Interrupt Timer
RLE
– Run Length Encoding
RSDS – Reduced-Swing Differential Signal interface
RTC
– Real Time Clock
SGM
– Sound Generator Module
SMC
– Stepper Motor Controller
SSD
– Stepper Stall Detect
STM
– System Timer Module
SWT
– Software Watchdog Timer
TCON – Timing Controller
VIU2
– Video Input Unit
VReg
– Voltage regulator
Figure 1. MPC5645S block diagram
Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8
4
Freescale Semiconductor