MPC8540(2004) 데이터 시트보기 (PDF) - Freescale Semiconductor
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MPC8540 Datasheet PDF : 1302 Pages
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Contents
Paragraph
Number
Title
Page
Number
12.4.2
12.4.3
12.4.4
12.4.4.1
12.4.4.2
12.4.4.3
12.4.5
12.4.5.1
12.4.5.2
12.4.5.3
12.5
Baud-Rate Generator Logic ..................................................................................... 12-22
Local Loop-Back Mode ........................................................................................... 12-22
Errors ....................................................................................................................... 12-23
Framing Error ...................................................................................................... 12-23
Parity Error .......................................................................................................... 12-23
Overrun Error....................................................................................................... 12-23
FIFO Mode .............................................................................................................. 12-24
FIFO Interrupts .................................................................................................... 12-24
DMA Mode Select ............................................................................................... 12-24
Interrupt Control Logic........................................................................................ 12-25
DUART Initialization/Application Information .......................................................... 12-25
13.1
13.1.1
13.1.2
13.1.3
13.1.3.1
13.1.3.2
13.1.4
13.1.5
13.2
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.2.1
13.3.1.2.2
13.3.1.2.3
13.3.1.2.4
13.3.1.3
13.3.1.4
13.3.1.5
13.3.1.6
13.3.1.7
13.3.1.8
13.3.1.9
13.3.1.10
Chapter 13
Local Bus Controller
Introduction.................................................................................................................... 13-1
Overview.................................................................................................................... 13-2
Features...................................................................................................................... 13-2
Modes of Operation ................................................................................................... 13-3
LBC Bus Clock and Clock Ratios ......................................................................... 13-4
Source ID Debug Mode ......................................................................................... 13-4
Power-Down Mode.................................................................................................... 13-4
References.................................................................................................................. 13-4
External Signal Descriptions ......................................................................................... 13-5
Memory Map/Register Definition ................................................................................. 13-9
Register Descriptions............................................................................................... 13-10
Base Registers (BR0–BR7) ................................................................................. 13-11
Option Registers (OR0–OR7).............................................................................. 13-12
Address Mask .................................................................................................. 13-13
Option Registers (ORn)—GPCM Mode ......................................................... 13-14
Option Registers (ORn)—UPM Mode ............................................................ 13-16
Option Registers (ORn)—SDRAM Mode ...................................................... 13-17
UPM Memory Address Register (MAR)............................................................. 13-18
UPM Mode Registers (MxMR) ........................................................................... 13-19
Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 13-21
UPM Data Register (MDR) ................................................................................. 13-22
SDRAM Machine Mode Register (LSDMR) ...................................................... 13-22
UPM Refresh Timer (LURT)............................................................................... 13-24
SDRAM Refresh Timer (LSRT).......................................................................... 13-25
Transfer Error Status Register (LTESR).............................................................. 13-26
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
xix
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