MPC951 데이터 시트보기 (PDF) - Motorola => Freescale

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MPC951

Low Voltage PLL Clock Driver

Motorola => Freescale 

MPC950 MPC951

PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)

Symbol

Characteristic

Min

Max

Unit

Condition

tr, tf

TCLK Input Rise/Falls

3.0

ns

fref

Reference Input Frequency

Note 1.

Note 1.

MHz

fXtal

Crystal Oscillator Frequency

10

25

MHz Note 2.

frefDC

Reference Input Duty Cycle

25

75

%

1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.

2. See Applications Info section for more crystal information.

AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

tr, tf

Output Rise/Fall Time

0.10

1.0

ns 0.8 to 2.0V

tpw

Output Duty Cycle

tCYCLE/2–1000

tCYCLE/2+1000 ps

tsk(O)

Output–to–Output Skews Same Frequencies

200

375

ps

Different Frequencies

Qafmax < 150MHz

Qafmax > 150MHz

325

500

750

fVCO

PLL VCO

Lock

Range

Feedback = VCO/4

200

Feedback = VCO/8

200

Feedback = VCO/16

200

480

MHz MPC951

480

MPC950 or 951

480

MPC950

fmax

Maximum Output

Frequency

Qa (÷2)

Qa/Qb (÷4)

Qb (÷8)

180

MHz

120

60

tpd

Input to Ext_FB Delay

(Note 1.)

TCLK

PECL_CLK

50

–950

250

–770

400

–600

ps fref = 50MHz

Feedback=VCO/8

tPLZ,HZ Output Disable Time

7

ns

tPZL

Output Enable Time

6

ns

tjitter

Cycle–to–Cycle Jitter (Peak–to–Peak)

±100

ps Note 2.

tlock

Maximum PLL Lock Time

10

ms

1. The specification is guaranteed for the MPC951 only. The tpd window is specified for a 50Mhz input reference clock. The window will

enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period.

2. See Applications Info section for more jitter information.

APPLICATIONS INFORMATION

Programming the MPC950/951

The MPC950/951 clock driver outputs can be configured

into several frequency relationships, in addition the external

feedback option of the MPC951 allows for a great deal of

flexibility in establishing unique input to output frequency

relationships. The output dividers for the four output groups

allows the user to configure the outputs into 1:1, 2:1, 4:1 and

4:2:1 frequency ratios. The use of even dividers ensures that

the output duty cycle is always 50%. Table 1 illustrates the

various output configurations, the table describes the outputs

using the VCO frequency as a reference. As an example for a

4:2:1 relationship the Qa outputs would be set at VCO/2, the

Qb’s and Qc’s at VCO/4 and the Qd’s at VCO/8. These

settings will provide output frequencies with a 4:2:1

relationship.

The division settings establish the output relationship, but

one must still ensure that the VCO will be stable given the

frequency of the outputs desired. The feedback frequency

should be used to situate the VCO into a frequency range in

which the PLL will be stable. The design of the PLL is such

that for output frequencies between 25 and 180MHz the

MPC950/951 can generally be configured into a stable

region.

The relationship between the input reference and the

output frequency is also very flexible. Table 2 shows the

multiplication factors between the inputs and outputs for the

MPC950. For external feedback (MPC951) Table 1 can be

used to determine the multiplication factor, there are too

many potential combinations to tabularize the external

feedback condition. Figure 1 through Figure 6 illustrates

several programming possibilities, although not exhaustive it

is representative of the potential applications.

TIMING SOLUTIONS

5

BR1333 — Rev 6

MOTOROLA

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