MPC970 데이터 시트보기 (PDF) - Motorola => Freescale

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MPC970

Low Voltage PLL Clock Driver

Motorola => Freescale 

MPC970

xtal1

xtal2

Ref_Sel

TClk

PLL_En

VCO_Sel

Ext_FB

IntFB_Sel

MPC601_CLKs

BClk_Div0

BClk_Div1

PCI_Div0

PCI_Div1

Frz_Data

Frz_Clk

Frz_Strobe

Com_Frz

MR/Tristate

PLL

Clock

Dividers

Freeze

Control

Register

Clock,

De–Skew,

Freeze

3–State

Drivers

2x_PCLK

PCLKEN

BCLKEN

BCLK0

BCLK1

BCLK2

BCLK3

BCLK4

PCI_CLK0

PCI_CLK1

PCI_CLK2

PCI_CLK3

PCI_CLK4

PCI_CLK5

PCI_CLK6

Figure 1. Enable/Disable Scheme

The MPC970 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug

as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines.

The MPC970 allows for the enabling of each output independently via a serial input port or a common enable/disable of all

outputs simultaneously via a parallel control pin. When disabled or “frozen” the outputs will be locked in the “LOW” state, however

the internal state machines will continue to run. Therefore when “unfrozen” the outputs will activate synchronous and in phase

with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only when they are already in the “LOW”

state, thus the possibility of runt pulse generation is eliminated. A power–on reset will ensure that upon power up all of the outputs

will be active.

For IC and board level testing a MR/Tristate input is provided. When pulled “LOW” all outputs will tristate and all internal flip

flops will be reset. In addition the internal PLL can be bypassed and the fanout dividers and output buffers can be driven directly

by the TClk input pin. Note that in this mode it will take a number of input clock pulses to cause output transitions as the TClk is

fed through the internal dividers.

The MPC970 is fully 3.3V (3.6V for PowerPC 601 designs) compatible and requires no external loop filter components. All

inputs accept LVCMOS/LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive 50Ω

transmission lines. For series terminated lines each MPC970 output can drive two 50Ω lines in parallel thus effectively doubling

the fanout of the device.

MOTOROLA

2

TIMING SOLUTIONS

BR1333 — Rev 6

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