MPC970 데이터 시트보기 (PDF) - Motorola => Freescale

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MPC970

Low Voltage PLL Clock Driver

Motorola => Freescale 

PLL_EN

TClk

Ref_Sel

xtal1

xtal2

Ext_FB

IntFB_Sel

VCO_Sel

MPC601_Clks

BCLK_Div0

BCLK_Div1

PCI_Div0

PCI_Div1

Frz_Strobe

Frz_Clk

Com_frz

Frz_Data

MR/Tristate

PLL

fVCO

fVCO/2

4x_pclk

÷2

2x_pclk

Clock

Dividers

pclk

bclk50dc

bclk>50dc

pci_clk

pci_pclk_enb

Serial

Input

Controller

Serial

Input

Register

2x_plck_frz

pclken_frz

bclken_frz

bclk0_frz

bclk1_frz

bclk2_frz

bclk3_frz

Mux

Freeze

Register

bclk4_frz

pci_clk0_frz

pci_clk1_frz

pci_clk2_frz

pci_clk3_frz

pci_clk4_frz

pci_clk5_frz

pci_clk6_frz

Figure 2. Simplified Block Diagram

MPC970

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

Freeze,

De–Skew

2x_PCLK

PCLKEN

BCLKEN

BCLK0

BCLK1

BCLK2

BCLK3

BCLK4

PCI_CLK0

PCI_CLK1

PCI_CLK2

PCI_CLK3

PCI_CLK4

PCI_CLK5

PCI_CLK6

TIMING SOLUTIONS

3

BR1333 — Rev 6

MOTOROLA

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