MPC9447 데이터 시트보기 (PDF) - Integrated Device Technology
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MPC9447 Datasheet PDF : 9 Pages
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MPC9447
3.3VM/2P.5CV914:94L7VCMOS Clock FanoutFBrueffeer scale Semiconductor, Inc.
NETCOM
CCLK0
CCLK1
CLK_SEL
CLK_STOP
0
1
VCC
CLK
STOP
VCC
SYNC
VCC
(all input resistors have a value of 25kΩ)
OE
Figure 1. Logic Diagram
Q0
24 23 22 21 20 19 18 17
Q1 GND
25
16
GND
Q2 Q2
26
VCC
27
Q3
Q1
28
Q4
GND
29
MPC9447
15
Q6
14
VCC
13
Q7
12
GND
Q5 Q0
30
11
Q8
Q6 VCC
31
10
VCC
GND
32
9
GND
Q7
12345678
Q8
Figure 2. 32--Lead Pinout (Top View)
Table 1. Function Table
Control
Default
CLK_SEL
1
OE
1
0
CLK0 input selected
Outputs disabled (high--impedance state)a
CLK_STOP
1
Outputs synchronously stopped in logic low state
a. OE = 0 will high--impedance tristate all outputs independent on CLK_STOP
1
CLK1 input selected
Outputs enabled
Outputs active
Table 2. Pin Configuration
Pin
I/O
CCLK0
Input
CCLK1
Input
CLK_SEL
Input
CLK_STOP
OE
Q0--8
GND
VCC
Input
Input
Output
Supply
Supply
Table 3. General Specifications
Symbol
Characteristics
VTT Output termination voltage
MM ESD protection (Machine model)
HBM ESD protection (Human body model)
LU Latch-up immunity
CPD Power dissipation capacitance
CIN Input capacitance
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
Function
Clock signal input
Alternative clock signal input
Clock input select
Clock output enable/disable
Output enable/disable (high--impedance tristate)
Clock outputs
Negative power supply (GND)
Positive power supply for I/O and core. All VCC pins must be
connected to the positive power supply for correct operation
Min
200
2000
200
Typ
VCC ÷ 2
10
4.0
Max
Unit Condition
V
V
V
mA
pF Per output
pF Inputs
IDT™ 3.M3VO/2T.O5RVO1L:9ALVCMOS Clock Fanout Buffer
2
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TIMING SOLUTIONS MPC9447
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