MPC905 데이터 시트보기 (PDF) - Integrated Device Technology

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MPC905

1:6 PCI Clock Generator/Fanout Buffer

Integrated Device Technology 

MPC905

1:6 PCI Clock Generator/Fanout BuffFerreescale Semiconductor, Inc.

MPC905

NETCOM

BCLK5

BCLK0–4

ENABLE2

ENABLE1

Figure 3. Enable Timing Diagram

APPLICATIONS INFORMATION

Driving Transmission Lines

The MPC905 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of approximately 10Ω

the drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091 in the

Timing Solutions data book (DL207/D).

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a

point–to–point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50Ω resistance to VCC/2. This technique draws a fairly high

level of DC current and thus only a single terminated line can

be driven by each output of the MPC905 clock driver. For the

series terminated case however there is no DC current draw,

thus the outputs can drive multiple series terminated lines.

Figure 4 illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC905 clock

driver is effectively doubled due to its capability to drive

multiple lines.

MPC905

OUTPUT

BUFFER

IN

10Ω

RS = 40Ω ZO = 50Ω

OutA

MPC905

OUTPUT

BUFFER

IN

10W

RS = 40Ω ZO = 50Ω

RS = 40Ω ZO = 50Ω

OutB0

OutB1

Figure 4. Single versus Dual Transmission Lines

The waveform plots of Figure 5 show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC905 output buffers is

more than sufficient to drive 50Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations a delta of only 43ps exists between the two

differently loaded outputs. The output waveform in Figure 5

IDT™ 1:6 PCI Clock Generator/Fanout Buffer

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MPC905

TIMING SOLUTIONS

DL207 — Rev 0

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