MS6266SSGU(REV2) 데이터 시트보기 (PDF) - MOSA ELECTRONICS
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MS6266SSGU
(Rev.:REV2)
(Rev.:REV2)
MOSA ELECTRONICS
MS6266SSGU Datasheet PDF : 13 Pages
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MOSA
Timing of SDA and SCL bus lines
SDA
tf
tLOW
tr
tSU;DAT
tf
SCL
MS6266
6-Channel Electronic Volume Controller
tHD;STA
tSP tr
tBUF
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
PS
Standard mode
Symbol
Parameter
Min Max Unit
fSCL
tHD:STA
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
0
100
kHz
4.0
-
us
tLOW
LOW period of the SCL clock
4.7
-
us
tHIGH HIGH period of the SCL clock
4.0
-
us
tSU:STA
tHD:DAT
Set-up time for a repeated START condition
Data hold time:
For I2C-bus devices
4.7
-
us
0
3.45
us
tSU:DAT Data-set-up time
250
-
ns
tr
Rise time of both SDA and SCL signals
-
1000
ns
tf
Fall time of both SDA and SCL signals
-
300
ns
tSU:STO Set-up time for STOP condition
4.0
-
us
tBUF
Bus free time between a STOP and START condition
4.7
-
us
Cb
Capacitive load for each bus line
-
400
pF
VnL
Noise margin at the LOW level for each connected device (including
hysteresis)
0.1VDD
-
V
VnH
Noise margin at the HIGH level for each connected device (including
hysteresis)
0.2VDD
-
V
REV 2
6/13
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