MS81V04160A 데이터 시트보기 (PDF) - Oki Electric Industry

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MS81V04160A

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Oki Electric Industry 

1Semiconductor

FEDS81V04160A-01

MS81V04160A

Data Input: (DIN20 to 27)

These pins are used for serial data inputs.

Write Reset: RSTW2

The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW2

setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely

controlled by the SWCK rising edge after the high level of RSTW2, the states of WE2 and IE2 are ignored in the

write reset cycle. Before RSTW2 may be brought high again for a further reset operation, it must be low for at least

two SWCK cycles.

Write Enable: WE2

WE is used for data write enable/disable control. WE2 high level enables the input, and WE2 low level disables the

input and holds the internal write address pointer. There are no WE2 disable time (low) and WE2 enable time

(high) restrictions, because the MS81V04160A is in fully static operation as long as the power is on. Note that

WE2 setup and hold times are referenced to the rising edge of SWCK.

Input Enable: IE2

IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The internal write address

pointer is always incremented by cycling SWCK regardless of the IE2 level. Note that IE2 setup and hold times are

referenced to the rising edge of SWCK.

Data Out: (DOUT20 to 27)

These pins are used for serial data outputs.

Read Reset: RSTR2

The first positive transition of SRCK after RSTR2 becomes high resets the read address pointers to zero. RSTR2

setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled

by the SRCK rising edge after the high level of RSTR2, the states of RE2 and OE2 are ignored in the read reset

cycle. Before RSTR2 may be brought high again for a further reset operation, it must be low for at least *two

SRCK cycles.

Output Enable: OE2

OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal read address pointer is

always incremented by cycling SRCK regardless of the OE2 level. Note that OE2 setup and hold times are

referenced to the rising edge of SRCK.

Mode Setting1: MODE1

The Cascade/Non cascade select pin. Setting the MODE1 pin to the VCC level configures this memory device as

cascade type and setting the pin to the VSS level configures this memory device as non cascade. During memory

operation, the pin must be permanently connected to VCC or VSS. If a MODE1 level is changed during memory

operation, memory data is not guaranteed.

Mode Setting2: MODE2

MODE2 selects whether the control input signals are enabled at a high level or a low level. Setting MODE2 to the

Vcc level enables the control input signals at a low level and setting MODE2 to the Vss level enables the control

input signals at a high level.

Note: Cascade/Non cascade

When MODE1 is set to the VSS level, memory accessing starts in the cycle in which the control signals are input

(Non cascade type). When MODE1 is set to the VCC level, memory accessing starts in the cycle subsequent to the

cycle in which the control signals are input (Cascade type). This type is used for consecutive memory accessing.

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