MSM514102D-60SJ 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM514102D-60SJ

4,194,304-Word x 1-Bit DYNAMIC RAM : STATIC COLUMN MODE TYPE

Oki Electric Industry 

¡ Semiconductor

MSM514102D/DL

Notes:

1. A start-up delay of 200 µs is required after power-up, followed by a minimum of

eight initialization cycles (RAS-only refresh or CS before RAS refresh) before proper

device operation is achieved.

2. The AC characteristics assume tT = 5 ns.

3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.

Transition times (tT) are measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.

tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified

tRCD (Max.) limit, then the access time is controlled by tCAC.

6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.

tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified

tRAD (Max.) limit, then the access time is controlled by tAA.

7. Operating within the tLWAD (Max.) limit ensures that tALW (Max.) can be met.

tLWAD (Max.) is specified as a reference point only. If tLWAD is greater than the

specified tLWAD (Max.) limit, then the access time is controlled by tAA.

8. tOFF (Max.) defines the time at which the output achieves the open circuit condition and

is not referenced to output voltage levels.

9. tRCH or tRRH must be satisfied for a read cycle.

10. tWCS, tCWD, tRWD and tAWD are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then

the cycle is an early write cycle and the data out will remain open circuit (high

impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.)

and tAWD ≥ tAWD (Min.), then the cycle is a read modify write cycle and data out will

contain data read from the selected cell; if neither of the above sets of conditions is

satisfied, then the condition of the data out (at access time) is indeterminate.

11. These parameters are referenced to the CS leading edge in an early write cycle, and

to the WE leading edge in a read modify write cycle.

12. The test mode is initiated by performing a WE and CS before RAS refresh cycle. This

mode is latched and remains in effect until the exit cycle is generated.

The test mode specified in this data sheet is an 8-bit parallel test function. RA10,

CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data

output pin will indicate a high level. If any internal bits are not equal, the data

output pin will indicate a low level.

The test mode is cleared and the memory device returned to its normal operating

state by performing a RAS-only refresh cycle or a CS before RAS refresh cycle.

13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the

specified value. These parameters should be specified in test mode cycle by adding the

above value to the specified value in this data sheet.

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