MSM514800D-60JS 데이터 시트보기 (PDF) - Oki Electric Industry

부품명

상세내역

제조사

MSM514800D-60JS

524,288-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE

Oki Electric Industry 

1Semiconductor

This Version: Dec.2000

FEDD514800DSL-01

MSM514800D/DSL

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization

cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.

2. The AC characteristics assume tT = 5ns.

3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times

(tT) are measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.

5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.

tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.)

limit, then the access time is controlled by tCAC.

6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.

tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.)

limit, then the access time is controlled by tAA.

7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit

condition and are not referenced to output voltage levels.

8. tRCH or tRRH must be satisfied for a read cycle.

9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in

the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early

write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.

If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then

the cycle is a read modify write cycle and data out will contain data read from the selected cell; if

neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)

is indeterminate.

10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE

leading edge in an OE control write cycle, or a read modify write cycle.

11. SL version only.

8/14

Share Link: