MSM5265 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM5265

80-DOT LCD DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM5265

FUNCTIONAL DESCRIPTION

Operational Description

The MSM5265 consists of a 160-stage shift register, 160-bit data latch, and 80 pairs of LCD

drivers. The display data is input from the DATA-IN pin to the 160-stage shift register at the

rising edge of the CLOCK pulse and it is shifted to the 160-bit data latch when the LOAD

signal is set at "H" level, then it is directly output from the 80 pairs of LCD drivers to the LCD

panel. Input the display data in the order of SEG80, SEG79, SEG78, ..., SEG2, SEG1.

DATA-IN

CLOCK

1

2

3

4

5

6 159

160

LOAD

DATA LATCH

Output

(inside the IC)

Pin Functional Description

• OSC-IN, OSC-OUT, OSC-OUT

As shown in the figure below, by connecting the external resistors R0, R1 and external

capacitor C0 with OSC-IN, OSC-OUT and OSC-OUT respectively, an oscillating circuit to

generate the common signal is formed.

This frequency is divided into either 1/8 or 1/4 by the internal dividing circuit. The 1/8

divided frequency is used in the static display mode, while the 1/4 divided frequency is used

as the common signal in the 1/2 duty dynamic display mode which is output from the COM-

OUT pin. (EXT/INT should be set at low level.)

The resistor R1 is used to limit the current on the OSC-IN pin's protecting diodes. The value

of the R1 should be more than 10 times that of R0.

When the external common signal is used, the EXT/INT pin should be set at high level and

the external common signal should be input from the OSC-IN pin.

Keep the wiring between the OSC-IN pin and R1 as short as possible, because the OSC-IN pin

becomes susceptible to external noise if the value of R1 is large.

R0

OSC-OUT

C0

OSC-OUT

(MSM5265)

fOSC = 1/2.2 C0R0

R1≥10 R0

VDD

R1

fOSC

OSC-IN

7/18

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