MSM6669 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM6669

80-DOT LCD SEGMENT DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM6669

FUNCTIONAL DESCRIPTION

Pin Functional Description

• EI, EO

These are enable signal input and output pins. When a cascade connection is required, set the

first MSM6669's EI pin at "L" level and connect the EO pin to the next MSM6669's EI pin. When

a single MSM6669 is used, EI should be set at "L" level.

• CP

This is a pin for clocking the display data in. Display data is stored into the latch (I) at the

falling edge of a clock pulse. A clock pulse through this pin is enabled when the enable F/

F is set, and disabled when it is not set.

• LOAD

This is an input pin to latch the display data of one line stored in the latch (I). At the falling

edge of a load pulse, the display data stored in the latch (I) is transferred to the latch (II). The

control circuit to save the power is reset and the display data on the next line can be stored.

• DF

Synchronous signal input pin for alternate signal for LCD driving.

• VDD, VSS

These are power supply pins of this IC. The VDD pin is generally set to 2.7 to 5.5V. VSS is a

grounding pin, which is generally set to 0V.

• O1 to O80

These are output pins of the 4-level driver of this IC, which correspond directly to the bits of

the 80-bit latch (II). One of the four levels V1, V3, V4, and VEE is selected and output by a

combination of the latch contents (display data) and a DF signal. See the truth table.

Connect the output pins to the liquid crystal panel on the segment side.

• DISP OFF

This is an input pin to control the output pins O1 to O80. During low signal input, signals on

the V1 level are output from the output pins O1 to O80 irrespective of display data. See the

truth table.

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