MSM7583 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM7583

π/4 Shift QPSK MODEM

Oki Electric Industry 

¡ Semiconductor

MSM7583

SG

Internal reference voltage output.

The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin

and the AGND pin. The external SG voltage, if necessary should be used via buffer.

RESET

Control register reset.

When this pin is set to "0", the register is reset to the initial value.

The reset signal input width is 200 ns or more.

PDN0, PDN1, PDN2

Inputs for power-down control.

PDN0 controls the standby/communication modes, PDN1 controls the modulator, and PDN2

controls the demodulator. Refer to Table 1 for details.

Table 1 Power Down Control

Standby Mode

PDN0 PDN1 PDN2

0

—

0

0

—

1

1

0

0

1

1

0

Communication

Mode

1

0

1

1

1

1

Function

All power-down.

Modulator power is off (VREF and PLL power is also off).

Demodulator power is on.

Modulator power is off (VREF and PLL power is on).

I and Q outputs are in a high-impedance state.

Only demodulator clock recovery block power is on.

Modulator power is on.

Only demodulator clock recovery block power is on.

Modulator power is off (VREF and PLL power is on).

I and Q outputs are in a high-impedance state.

Demodulator power is on.

Modulator power is on.

Demodulator power is on.

Mode

Mode A

Mode B

Mode C

Mode D

Mode E

Mode F

VDD

+5 V power supply voltage.

AGND

Analog signal ground.

DGND

Digital signal ground.

AGND and DGND are not connected in the device. This pin should be tied to the AGND pin

on the PCB as close as possible from the device.

AGND and DGND should be connected as close as prossible on the PC board.

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