MSM9000-XX 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM9000-XX

DOT MATRIX LCD CONTROLLER

Oki Electric Industry 

¡ Semiconductor

FEDL9000B-01

MSM9000B-xx

N1

N2

Contrast adjustment range by command

L

L

0 to 7

L

H

1 to 8

H

L

2 to 9

H

H

3 to A

• TEST (Test Signal)

Test signal input pin provided for test by the manufacturer. Fix this pin to L or leave it open.

• SEG1 to SEG60 (Segment 1 to Segment 60)

Segment signal output pins to drive the LCD. Leave the unused pins open.

• COM1 to COM16 (Common 1 to Common 16)

Common signal output pins to drive the LCD. When the duty cycle is 1/9, use COM1 to COM9

and leave COM10 to COM16 open.

• VDD

Power supply pin to the logic section. Connect this pin to the positive terminal on the power

supply.

• VSS

Pin to be connected to the GND power supply.

• VSS1, VSS4, VSS5

Pins for voltage multiplier outputs and LCD power supply. Connect capacitors of 0.1 µF

between these pins and VDD for the charge distribution with VSS2, 3 capacitor and for voltage

stabilization during generation of LCD bias voltages. The logical values of the LCD bias

voltage are as follows:

Highest voltage: VDD

VSS1=VSS2, 3/2

VSS2, 3

VSS4=VSS2, 3+VSS2, 3/2

Lowest voltage: VSS5=VSS2, 3+VSS2, 3/2+VSS2, 3/2

For both the 1/9 and 1/16 duty, 1/4 bias is used.

• VSS2, 3

Voltage regulator output pin & LCD bias generator input used as a reference voltage for the

LCD bias generator.

Connect a capacitor of 0.1 µF between this pin and VDD for charge distribution among

capacitors and voltage stabilization during generation of various LCD bias voltages.

• VSS6

Pin to connect the capacitor to store the 3-/2-fold voltage. Connect a capacitor of 0.1µF or more

between this pin and VDD.

• VSH

Halves output pin for the voltage multiplier(3-/2-fold). Connect a 0.1 µF capacitor between

this pin and VDD.

13/39

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