M95160-RMN1 데이터 시트보기 (PDF) - STMicroelectronics

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M95160-RMN1

64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95640, M95320, M95160, M95080

Figure 4. Data and Clock Timing

CPOL CPHA

0

0

C

1

1

C

D or Q

MSB

LSB

AI01438

a part of the memory, using the BPn bits of the sta-

tus register, in the Software Protected Mode

(SPM).

Hold (HOLD)

The HOLD pin is used to pause the serial commu-

nications between the SPI memory and controller,

without losing bits that have already been decoded

in the serial sequence. For a hold condition to oc-

cur, the memory device must already have been

selected (S = 0). The hold condition starts when

the HOLD pin is held low while the clock pin (C) is

also low (as shown in Figure 14).

During the hold condition, the Q output pin is held

in its high impedance state, and the levels on the

input pins (D and C) are ignored by the memory

device.

It is possible to deselect the device when it is still

in the hold state, thereby resetting whatever trans-

fer had been in progress. The memory remains in

the hold state as long as the HOLD pin is low. To

restart communication with the device, it is neces-

sary both to remove the hold condition (by taking

HOLD high) and to select the memory (by taking S

low).

OPERATIONS

All instructions, addresses and data are shifted se-

rially in and out of the chip. The most significant bit

is presented first, with the data input (D) sampled

on the first rising edge of the clock (C) after the

chip select (S) goes low.

Every instruction starts with a single-byte code, as

summarised in Table 4. This code is entered via

the data input (D), and latched on the rising edge

of the clock input (C). To enter an instruction code,

the product must have been previously selected (S

held low). If an invalid instruction is sent (one not

contained in Table 4), the chip automatically dese-

lects itself.

Write Enable (WREN) and Write Disable (WRDI)

The write enable latch, inside the memory device,

must be set prior to each WRITE and WRSR oper-

ation. The WREN instruction (write enable) sets

this latch, and the WRDI instruction (write disable)

resets it.

The latch becomes reset by any of the following

events:

– Power on

– WRDI instruction completion

– WRSR instruction completion

– WRITE instruction completion.

Table 3. Write Protection Control on the M95640, M95320, M95160, M95080

W

SRWD

Bit

Mode

Status Register

Data Bytes

Protected Area

Unprotected Area

0 or 1

0

Software Writeable (if the WREN Software write protected Writeable (if the WREN

Protected instruction has set the

by the BPn of the status

instruction has set the

1

1

(SPM)

WEL bit)

register

WEL bit)

Hardware

Hardware write protected Writeable (if the WREN

0

1

Protected Hardware write protected

by the BPn bits of the

instruction has set the

(HPM)

status register

WEL bit)

4/19

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