M95160-RMN1 데이터 시트보기 (PDF) - STMicroelectronics
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M95160-RMN1 Datasheet PDF : 19 Pages
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M95640, M95320, M95160, M95080
Figure 8. Read EEPROM Array Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
C
INSTRUCTION
16 BIT ADDRESS
D
15 14 13 3 2 1 0
HIGH IMPEDANCE
Q
DATA OUT
76543210
MSB
AI01793
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Table 7. Address Range Bits
Device M95640 M95320 M95160 M95080
Address Bits A12-A0 A11-A0 A10-A0 A9-A0
Note: 1. Address bits up to b15 are treated as Don’t Care.
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S low. The se-
rial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).
The data stored in the memory, at the selected ad-
dress, is shifted out on the Q output pin. Each bit
is shifted out during the falling edge of the clock
(C) as shown in Figure 8. The internal address
counter is automatically incremented to the next
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
next address, can be read by successive clock
pulses. When the highest address is reached, the
address counter rolls over to “0000h”, allowing the
read cycle to be continued indefinitely. The read
operation is terminated by deselecting the chip.
The chip can be deselected at any time during
data output. If a read instruction is received during
a write cycle, it is rejected, and the memory device
deselects itself.
Byte Write Operation
Before any write can take place, the WEL bit must
be set, using the WREN instruction. The write
state is entered by selecting the chip, issuing three
bytes of instruction and address, and one byte of
data. Chip Select (S) must remain low throughout
the operation, as shown in Figure 10. The product
must be deselected just after the eighth bit of the
Figure 9. Write Enable Latch Sequence
S
01234567
C
8/19
D
HIGH IMPEDANCE
Q
AI02281
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