M95160-RMN1 데이터 시트보기 (PDF) - STMicroelectronics

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M95160-RMN1

64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95640, M95320, M95160, M95080

Figure 10. Byte Write Operation Sequence

S

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

C

INSTRUCTION

16 BIT ADDRESS

DATA BYTE

D

15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

HIGH IMPEDANCE

Q

Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

AI01795

data byte has been latched in, as shown in Figure

10, otherwise the write process is cancelled. As

soon as the memory device is deselected, the self-

timed internal write cycle is initiated. While the

write is in progress, the status register may be

read to check the status of the SRWD, BP1, BP0,

WEL and WIP bits. In particular, WIP contains a ‘1’

during the self-timed write cycle, and a ‘0’ when

the cycle is complete, (at which point the write en-

able latch is also reset).

Page Write Operation

A maximum of 32 bytes of data can be written dur-

ing one Write time, tW, provided that they are all to

Figure 11. Page Write Operation Sequence

S

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

C

INSTRUCTION

16 BIT ADDRESS

DATA BYTE 1

D

15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

S

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

C

DATA BYTE 2

DATA BYTE 3

DATA BYTE N

D

7654321076543210

6543210

Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

AI01796

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