X25642FI-2.7 데이터 시트보기 (PDF) - Xicor -> Intersil

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X25642FI-2.7

Advanced SPI Serial E2PROM with Block Lock™ Protection

Xicor -> Intersil 

X25642

Operational Notes

The X25642 powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

• SO pin is high impedance.

• The “write enable” latch is reset.

Data Protection

The following circuitry has been included to prevent in-

advertent writes:

• The “write enable” latch is reset upon power-up.

• A WREN instruction must be issued to set the “write

enable” latch.

• CS must come HIGH at the proper clock count in or-

der to start a write cycle.

Figure 1. Read E2PROM Array Operation Sequence

CS

SCK

0 1 2 3 4 5 6 7 8 9 10

20 21 22 23 24 25 26 27 28 29 30

INSTRUCTION

16 BIT ADDRESS

SI

15 14 13

3210

HIGH IMPEDANCE

SO

DATA OUT

76543210

MSB

3132 ILL F03.1

Figure 2. Read Status Register Operation Sequence

CS

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

INSTRUCTION

SI

HIGH IMPEDANCE

SO

76

MSB

DATA OUT

5432

10

3132 ILL F04

5

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