MT46H16M32LF 데이터 시트보기 (PDF) - Micron Technology
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MT46H16M32LF Datasheet PDF : 96 Pages
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512Mb: x16, x32 Mobile LPDDR SDRAM
Power-Down
Figure 51: Power-Down Mode (Active or Precharge)
T0
T1
T2
Ta0
Ta1
Ta2
Tb1
CK#
((
))
CK
((
tCK
tCH
tCL
))
tIS tIH
tIS
tCKE
tCKE1
CKE
((
))
tIS tIH
((
Command
Valid2
NOP
))
((
tIS tIH
))
((
Address
Valid
))
((
))
NOP
tXP1
((
DQS
))
((
))
((
DQ
))
((
))
((
DM
))
((
))
Must not exceed refresh device limits
No read/write
Enter3
access in progress power-down
mode
Exit
power-down
mode
Valid
Valid
Don’t Care
Notes:
1. tCKE applies if CKE goes LOW at Ta2 (entering power-down); tXP applies if CKE remains
HIGH at Ta2 (exit power-down).
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if
at least 1 row is already active), then the power-down mode shown is active power-
down.
3. No column accesses can be in progress when power-down is entered.
Deep Power-Down
Deep power-down (DPD) is an operating mode used to achieve maximum power reduc-
tion by eliminating power to the memory array. Data will not be retained after the de-
vice enters DPD mode.
Before entering DPD mode the device must be in the all banks idle state with no activity
on the data bus (tRP time must be met). DPD mode is entered by holding CS# and WE#
LOW with RAS# and CAS# HIGH at the rising edge of the clock while CKE is LOW. CKE
must be held LOW to maintain DPD mode. The clock must be stable prior to exiting
DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com-
mand present on the command bus. After exiting DPD mode, a full DRAM initialization
sequence is required.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
93
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© 2009 Micron Technology, Inc. All rights reserved.
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