MT46H16M32LF 데이터 시트보기 (PDF) - Micron Technology
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MT46H16M32LF Datasheet PDF : 96 Pages
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512Mb: x16, x32 Mobile LPDDR SDRAM
Clock Change Frequency
Clock Change Frequency
One method of controlling the power efficiency in applications is to throttle the clock
that controls the device. The clock can be controlled by changing the clock frequency or
stopping the clock.
The device enables the clock to change frequency during operation only if all timing pa-
rameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be
completed before entering clock stop mode; this includes the following timings: tRCD,
tRP, tRFC, tMRD, tWR, and tRPST. In addition, any READ or WRITE burst in progress
must be complete. (See READ Operation and WRITE Operation.)
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued.
Figure 53: Clock Stop Mode
CK#
CK
CKE
Command
Address
DQ, DQS
Ta1
((
))
((
))
((
))
((
))
((
NOP1
))
((
))
((
))
((
))
((
))
Ta2
CMD2
Valid
Tb3
Tb4
((
))
((
))
((
((
))
))
((
))
((
))
((
(
)
(
)CMD2
))
((
))
((
Valid
))
((
))
((
))
NOP
((
NOP
))
((
))
((
))
((
))
((
))
((
))
All DRAM activities must be complete
Exit clock stop mode
Enter clock stop mode
Don’t Care
Notes: 1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before
issuing any valid command.
2. Any valid command is supported; device is not in clock suspend mode.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
95
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© 2009 Micron Technology, Inc. All rights reserved.
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