MT48H16M16LFBF-8L 데이터 시트보기 (PDF) - Micron Technology
부품명
상세내역
제조사
MT48H16M16LFBF-8L Datasheet PDF : 71 Pages
| |||
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Functional Block Diagrams
The 256Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto
refresh mode is provided, along with a power-saving deep power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAM offers substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
Functional Block Diagrams
Figure 2: 16 Meg x 16 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
EXT MODE
REGISTER
MODE REGISTER
15
A0–A12,
BA0, BA1
15 ADDRESS
REGISTER
BA1
BA0
Bank
0
0
0
0
1
1
1
0
2
1
1
3
Bank3
Bank2
Bank1
REFRESH 13
COUNTER
ROW-
13
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8,192
BANK0
MEMORY
ARRAY
(8,192 x 512 x 16)
Sense amplifiers
8,192
2
BANK
CONTROL
2
LOGIC
COLUMN-
ADDRESS
9
9
COUNTER/
LATCH
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
256
(x16)
COLUMN
DECODER
2
2
DATA
16
OUTPUT
REGISTER
16
DATA
16
INPUT
REGISTER
UDQM,
LDQM
DQ0–
DQ15
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Share Link: 