MT88L85 데이터 시트보기 (PDF) - Mitel Networks

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MT88L85

3V Integrated DTMF Transceiver with Power Down & Adaptive Micro Interface

Mitel Networks 

Advance Information

MT88L85

BIT NAME

DESCRIPTION

b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.

When activated, the digital code representing a DTMF signal (see Table 1) can be written

to the transmit register, which will result in a transmit DTMF tone burst and pause of equal

durations (typically 51 msec). Following the pause, the status register will be updated (b1 -

Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been

enabled.

When CP mode (control register A, b1) is enabled the normal tone burst and pause

durations are extended from a typical duration of 51 msec to 102 msec.

When BURST is high (de-activated) the transmit tone burst duration is determined by the

TOUT bit (control register A, b0).

b1

RxEN This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both

circuits. A logic high deactivates and puts both receiver circuits into power down mode.

b2

S/D

Single or Dual Tone Generation. A logic high selects the single tone output; a logic low

selects the dual tone (DTMF) output. The single tone generation function requires further

selection of either the row or column tones (low or high group) through the C/R bit (control

register B, b3).

b3

C/R

Column or Row Tone Select. A logic high selects a column tone output; a logic low selects

a row tone output. This function is used in conjunction with the S/D bit (control register B,

b2).

Table 7. Control Register B Description

BIT

NAME

STATUS FLAG SET

STATUS FLAG CLEARED

b0

IRQ

b1 TRANSMIT DATA

REGISTER EMPTY

(BURST MODE ONLY)

Interrupt has occurred. Bit one

(b1) or bit two (b2) is set.

Pause duration has terminated

and transmitter is ready for new

data.

Interrupt is inactive. Cleared after

Status Register is read.

Cleared after Status Register is

read or when in non-burst mode.

b2 RECEIVE DATA REGISTER Valid data is in the Receive Data Cleared after Status Register is

FULL

Register.

read.

b3 DELAYED STEERING

Set upon the valid detection of

the absence of a DTMF signal.

Cleared upon the detection of a

valid DTMF signal.

Table 8. Status Register Description

4-81

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