MT88L85 데이터 시트보기 (PDF) - Mitel Networks
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MT88L85 Datasheet PDF : 20 Pages
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MT88L85
Advance Information
IN+ 1
IN- 2
GS 3
VRef 4
VSS 5
OSC1 6
OSC2 7
NC 8
NC 9
TONE 10
R/W/WR 11
CS 12
24 VDD
23 St/GT
22 ESt
21 D3
20 D2
19 D1
18 D0
17 NC
16 PWDN
15 IRQ/CP
14 DS/RD
13 RS0
•
NC 5
25 NC
VRef 6
24 D3
VSS 7
23 D2
OSC1 8
22 D1
OSC2 9
21 D0
NC 10
20 NC
NC 11
19 PWDN
24 PIN DIP/SSOP
28 PIN PLCC
Pin Description
Figure 2 - Pin Connections
Pin #
24 28
Name
Description
11
IN+ Non-inverting op-amp input.
2 2 IN- Inverting op-amp input.
34
GS Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
46
57
68
VRef
VSS
OSC1
Reference Voltage output (VDD/2).
Ground (0V).
Oscillator input. This pin can also be driven directly by an external clock.
7 9 OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
10 12 TONE Output from internal DTMF transmitter.
11 13 R/W(WR) (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
12 14
CS Chip Select input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
13 15 RS0 Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible.
14 17 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only
required when the device is being accessed. CMOS compatible.
15 18
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
16 19 PWDN Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ
and TONE output are high impedance. Data bus is held in tri-state. This pin is internally
pulled down.
14- 18- D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
17 21
(Intel). TTL compatible.
18 22
ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23
St/GT
Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 VDD Positive power supply (3V typ.).
4-72
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