MT8952BE 데이터 시트보기 (PDF) - Mitel Networks

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MT8952BE

ISO-CMOS ST-BUS™ FAMILY HDLC Protocol Controller

Mitel Networks 

ISO-CMOS MT8952B

Order of Bit Transmission/Reception

The Least Significant Bit (LSB) corresponding to D0

on the data bus is transmitted first on the serial

output (CDSTo). On the receiving side, the first bit

received on the serial input (CDSTi) is considered as

the LSB and placed on D0 of the data bus.

Registers

There are several registers in the HDLC Protocol

Controller accessible to the associated micro-

processor via the data bus. The addresses of these

registers are given in Table 1 and their functional

details are given below.

FIFO Status Register (Read):

This register (Figure 4) indicates the status of

transmit and receive FIFOs and the received byte as

described below.

D7 D6 D5 D4 D3 D2 D1 D0

Rx Byte

Status

Rx FIFO

Status

Tx FIFO

Status

LOW LOW

Figure 4 - FIFO Status Register

Rx Byte Status: These two bits (D7 and D6) indicate

the status of the received byte ready to be read from

the receive FIFO. The status is encoded as shown in

Table 3.

Rx Byte

Status Bits

D7 D6

Status

0

0 Packet Byte

0

1 First Byte

1

0 Last Byte (Good FCS)

1

1 Last Byte (Bad FCS)

Table 3. Received Byte Status

Rx FIFO Status: These bits (D5 and D4) indicate the

status of receive FIFO as given by Table 4. The Rx

FIFO status bits are not updated immediately after

an access of the Rx FIFO (a read from the

microprocessor port, or a write from the serial port),

to avoid the existence of unrecoverable error

conditions.

When in external timing mode, the MT8952B must

receive two falling edges of the clock signal at the

CKi input before the Rx FIFO status bits will be

updated. When in internal 2.048 MHz timing mode,

the MT8952B must receive two falling edges of the

C2i clock before the Rx FIFO status bits will be

Rx FIFO

Status Bits

D5 D4

Status

0

0 Rx FIFO Empty

0

1 Less than or equal to 14 bytes

1

0 Rx FIFO Full

1

1 Greater than or equal to 15 bytes

Table 4. Receive FIFO Status

updated. When in internal 4.096 MHz timing mode,

the MT8952B must receive four falling edges of the

C4i clock before the Rx FIFO status bit will be

updated (see the section on Receive Operation -

Normal Packets).

Tx FIFO Status: These two bits (D3 and D2) indicate

the status of transmit FIFO as shown in Table 5.

Tx FIFO

Status Bits

D3 D2

Status

0

0 Tx FIFO Full

0

1 Greater than or equal to 5 bytes

1

0 Tx FIFO Empty

1

1 Less than or equal to 4 bytes

Table 5. Transmit FIFO Status

The Tx FIFO status bits are updated in the same

manner as the Rx FIFO bits, except that in external

timing mode, and in internal 2.048 Mbps timing

mode, the Tx FIFO status bits are updated after two

falling edges of the CKi or the C2i signal (see the

section on Transmit Operation - Normal Packets).

Receive Data Register (Read):

Reading the Receive Data Register (Figure 5) puts

the first byte from the receive FIFO on the data bus.

The first bit of the data received on the serial input

(CDSTi) is considered to be the LSB and is available

on D0 of the data bus.

D7 D6 D5 D4 D3 D2 D1 D0

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Figure 5 - Receive Data Register

Transmit Data Register (Write):

Writing to Transmit Data Register (Figure 6) puts the

data present on the data bus into the transmit FIFO.

The LSB (D0) is transmitted first.

3-67

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