PDM31532SA10TA 데이터 시트보기 (PDF) - Paradigm Technology

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PDM31532SA10TA

64K x 16 CMOS 3.3V Static RAM

Paradigm Technology 

Read Timing Diagram

ADDRESSES

CE

OE

UB, LB

DOUT

PDM31532

tRC

tAA

tACE

tAOE

tBA

tLZBE(5)

tLZOE(5)

tLZCE(5)

tOH

tHZCE(5)

tHZOE(5)

tHZBE(5)

Output Data Valid

AC Electrical Characteristics

Description

-9 (7)

–10 (7)

–12

–15

–20

READ Cycle

READ cycle time

Address access time

Chip enable access time

Byte access time

Output hold from address change

Byte disable to output in low-Z

Byte enable to output in high-Z

Chip enable to output in low-Z(1, 5)

Chip disable to output high-Z(1, 5)

Output enable access time

Output enable to output in low-Z(1, 5)

Output disable to output in high-Z(1, 5)

Symbol Min Max Min Max Min Max Min Max Min Max Unit

tRC

9 — 10 — 12 — 15 — 20 — ns

tAA

— 9 — 10 — 12 — 15 — 20 ns

tACE

—

9

— 10 — 12 — 15 — 20 ns

tBA

— 6 — 6 — 7 — 8 — 9 ns

tOH

3 — 3 — 3 — 3 — 3 — ns

tLZBE

0—

0—

0

—0

—0

— ns

tHZBE

—

7

—

7

—

8

—

9

—

9

ns

tLZCE

3

—

3

—

3

—

3

—

3

— ns

tHZCE

—

6

—

6

—

7

—

8

—

9

ns

tAOE

—

6

—

6

—

7

—

8

—

9

ns

tLZOE

0

—

0

—

0

—

0

—

0

— ns

tHZOE

—

6

—

6

—

7

—

8

—

9

ns

6

Rev. 4.3 - 3/27/98

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