MT9072AB 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9072AB

Octal T1/E1/J1 Framer

Zarlink Semiconductor Inc 

T1/J1 Mode

• Operates at 4 kbit/s (FDL), 56 kbit/s or

64 kbit/s

MT9072

Data Sheet

E1 Mode

• Operates at 4, 8, 12, 16 or 20 kbit/s (Sa bits)

or 64 kbit/s

Common Channel Signaling Timeslot Assigner

• Selected 64 Kbit/s CCS channels (for V5.2 and GR-303) can be routed to/from an external multichannel

HDLC, using the CSTi/0 pins

Access and Monitoring for National (Sa) Bits (E1 mode only)

• In addition to the datalink functions, the Sa bits can be accessed using:

• Single byte register

• Five byte transmit and receive national bit buffers

• A maskable interrupt is generated on the change of state of any Sa bit

Slip Buffers

T1/J1 Mode

Transmit Slip Buffer

• Two-frame slip buffer capable of performing a

controlled slip. Intended for rate conversion in

the transmit direction

• Programmable delay

• Transmit slips are independent of receive slips

E1 Mode

Receive Slip Buffer

• Two-frame slip buffer capable of performing a

controlled slip

• Wander tolerance of 208 UI peak-to-peak

• Indication of slip

• Indication of slip direction

• Indication of slip

• Indication of slip direction

Receive Slip Buffer

• Two-frame slip buffer capable of performing a

controlled slip

• Wander tolerance of 142 UI (92 µs) peak

• Indication of slip

• Indication of slip direction

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Zarlink Semiconductor Inc.

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