MT9085 데이터 시트보기 (PDF) - Mitel Networks

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MT9085

CMOS PAC - Parallel Access Circuit

Mitel Networks 

MT9085 CMOS

In the example configuration shown in Figure 9 the

OE pin of PAC #2 is connected to D10 on the

Connection Memory. Setting bit 10 high in the

Connection Memory location corresponding to a

serial channel timeslot will result in the output driver

for the specific stream being disabled during that

serial channel timeslot. D11 is connected to the ME

input of SMX1 and D12 is connected to a mode

select pin (Mz). Consequently, the levels on these

outputs can be set high or low by writing to the

appropriate memory location corresponding to the

selected output channel. The mapping of the control

functions on to Connection Memory data bits is

illustrated in Figure 10.

The data on the PAC serial streams is byte

interleaved as described in the Functional

Description section in this data sheet. The SMX

channel number corresponding to the channel on the

serial streams can be determined directly by

specifying the serial channel and stream number in

binary as shown in Figure 11. For example, serial

channel 4, stream 2 corresponds to SMX channel

number Hex 0082. In order to program the matrix for

switching, the input channel address is written to the

Connection Memory address corresonding to the

serial output channel. The bits controlling features

such as OE, ME, and Mz should be set or reset

accordingly at the same time. For example. if

channel 4 on stream 2 is to be switched to channel

10 on stream 1, the following binary word is written

to Connection Memory address corresponding to the

output channel (Hex 0141):

XXX0 0000 1000 0010

Stream Address

Channel Address

Output Enable

Message Enable

DM-1/DM-2

Unused

Timing

Source

C16

C4

F0

F0i C4i C16i

S0

••••

S31

S0

••••

S31

2/4S

PAC#1

S/P

P0-P7

DFPo

CFPo

OE CKD MCA MCB

+5

SMX #1

DM - 1/2

8

8

D0-D7i

D0-D7o

C16

CK

FP

DATA

Mx

Mz MEMORY My

+5

R/W

CS

DS

ODE A0-A9 ME

10

From Timing Source

F0 C4 C16

F0i C4i C16i

PAC#2

P/S

P0-P7

S0

•••• ••••

S0

S31

S31

2/4S

OE CKD MCA MCB

+5

D12

D0-D9 D11

SMX #2 D10

CM - 1

ODE

+5

FP

Mx

CONNECTION My

+5

MEMORY

Mz

C16

CK

2-134

MPU Interface

NOTE: Connect all inputs not shown to VSS

Figure 9 - 1024 Channel Switch Matrix Using the PAC and SMX

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