MT9173 데이터 시트보기 (PDF) - Mitel Networks
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MT9173 Datasheet PDF : 22 Pages
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MT9173/74
Preliminary Information
determine which of the DNICs is using the externally
supplied clock and which is phase locking to the data
on the line. Due to jitter and end to end delay, one
end must be the master to generate all the timing for
the link and the other must extract the timing from
the receive data and synchronize itself to this timing
in order to recover the synchronous data. DUAL port
mode allows the user to use two separate serial
busses: the DV port for PCM/data (B channels) and
the CD port for control and signalling information (C
and D channels). In the SINGL port mode, all four
channels are concatenated into one serial stream
and input to the DNIC via the DV port. The order of
the C and D channels may be changed only in DN/
DUAL mode. The DNIC may be configured to
transfer the D-channel in channel 0 and the C-
channel in channel 16 or vice versa. One other
feature exists; ODE, where both the DV and CD
ports are tristated in order that no devices are
damaged due to excessive loading while all DNICs
are in a random state on power up in a daisy chain
arrangement.
DV Port (DSTi/Di, DSTo/Do)
The DV port transfers data or PCM encoded voice to
and from the line according to the particular mode
selected by the mode select pins. The modes
affecting the configuration of the DV port are MOD or
DN and DUAL or SINGL. In DN mode the DV port
operates as an ST-BUS at 2.048 Mbit/s with 32, 8 bit
channels per frame as shown in Figure 9. In this
mode the DV port channel configuration depends
upon whether DUAL or SINGL port is selected.
When DUAL port mode is used, the C and D
channels are passed through the CD port and the B1
and B2 channels are passed through the DV port. At
80 kbit/s only one channel of the available 32 at the
DV port is utilized, this being channel 0 which carries
the B1-channel. This is shown in Figure 3. At 160
kbit/s, two channels are used, these being 0 and 16
carrying the B1 and B2 channels, respectively. This
is shown in Figure 4. When SINGL port mode is
used, channels B1, B2, C and D are all passed via
the DV port and the CD port is disabled. See CD port
description for an explanation of the C and D
channels.
The D-channel is always passed during channel time
0 followed by the C and B1 channels in channel
times 1 and 2, respectively for 80 kbit/s. See Figure
5. For 160 kbit/s the B2 channel is added and
occupies channel time 3 of the DV port. See Figure
6. For all of the various configurations the bit orders
are shown by the respective diagram. In MOD mode
the DV and CD ports no longer operate at 2.048
Mbits/s but are continuous serial bit streams
operating at the bit rate selected of 80 or 160 kbit/s.
While in the MOD mode only DUAL port operation
can be used.
In order for more than one DNIC to be connected to
any one DV and CD port, making more efficient use
of the busses, the DSTo and CDSTo outputs are put
into high impedance during the inactive channel
times of the DNIC. This allows additional DNICs to
be cascaded onto the same DV and CD ports. When
used in this way a signal called F0o is used as an
indication to the next DNIC in a daisy chain that its
channel time is now active. Only the first DNIC in the
chain receives the system frame pulse and all
others receive the F0o from its predecessor in
the chain. This allows up to 16 DNICs to be
cascaded.
CD Port (CDSTi/CDi, CDSTo/CDo)
The CD port is a serial bidirectional port used only in
DUAL port mode. It is a means by which the DNIC
receives its control information for things such as
setting the bit rate, enabling internal loopback tests,
sending status information back to the system and
transferring low speed signalling data to and from the
line.
The CD port is composed of the C and D-Channels.
The C-channel is used for transferring control and
status information between the DNIC and the
system. The D-channel is used for sending and
F0
ST-BUS
Channel Channel Channel Channel
31
0
1
2
125 µsec
••••••••
Channel Channel
29
30
Channel Channel
31
0
9-146
Most
Significant
Bit (First)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
3.9 µsec
Figure 9 - ST-BUS Format
Bit 2
Bit 1
Bit 0
Least
Significant
Bit (Last)
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