MT9161BN 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT9161BN Datasheet PDF : 30 Pages
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MT9160B/61B
Advance Information
MT9160BS/BN
MT9160BE
MT9161BE/BS/BN
VBias 1
VRef 2
PWRST 3
IC 4
A/µ/IRQ 5
VSSD 6
CS 7
SCLK 8
DATA1 9
DATA2 10
20 M +
19 M -
18 VSSA
17 HSPKR +
16 HSPKR -
15 VDD
14 CLOCKin
13 STB/F0i
12 Din
11 Dout
20 PIN SOIC/SSOP
Pin Description
VBias 1
VRef 2
NC 3
PWRST 4
IC 5
A/µ/IRQ 6
VSSD 7
CS 8
NC 9
SCLK 10
DATA1 11
DATA2 12
24 M +
VBias 1
23 M -
VRef 2
22 VSSA
NC 3
21 NC
PWRST 4
20 HSPKR +
IC 5
19 HSPKR - A/µ/IRQ 6
18 VDD
VSSD 7
17 CLOCKin
CS 8
16 NC
NC 9
15 STB/F0i
SCLK 10
14 Din
DATA1 11
13 Dout
DATA2 12
24 M +
23 M -
22 VSSA
21 NC
20 HSPKR +
19 HSPKR -
18 VDD
17 CLOCKin
16 STBd/FOod
15 STB/F0i
14 Din
13 Dout
24 PIN PDIP
24 PIN PDIP/SOIC/SSOP
Figure 2 - Pin Connections
Pin # Pin #
20 Pin 24 Pin
1
1
2
2
3
4
4
5
5
6
6
7
7
8
8
10
9
11
10
12
11
13
12
14
Name
Description
VBias
VRef
PWRST
Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1 µF capacitor to VSSA,Connect 1 µF capacitor to Vref.
Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used
internally. Connect 0.1 µF capacitor to VSSA,Connect 1 µF capacitor to VBias.
Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
Resets internal state of device.
IC
A/µ/IRQ
Internal Connection. Tie externally to VSSD for normal operation.
A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin
governs the companding law used by the filter/Codec; µ-Law when tied to VSSD and
A-Law when tied to VDD. Logically OR’ed with A/µ register bit.
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
VSSD
CS
Digital Ground. Nominally 0 volts.
Chip Select (Input). This input signal is used to select the device for microport
data transfers. Active low. CMOS level compatible.
SCLK Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level
compatible.
DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.
DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
Dout Data Output. A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.
Din Data Input. A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
80
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