MT9160B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9160B

ISO²-CMOS 5 Volt Multi-Featured Codec (MFC) Advance Information

Zarlink Semiconductor Inc 

Advance Information

MT9160B/61B

IRQ

Microport Read/Write Access

FP

n-3

n-2

n-1

n

n+1

n+2

n+3

n+4*

DSTo/

DSTi

Di-bit Group

Receive

D-Channel

I

D0

II

III

D1 D2

D3 D4

No preset value

IV

D5 D6

D7

Di-bit Group

I

Transmit D0

D-Channel

II

III

IV

D1 D2

D3 D4

D5 D6

D7

Power-up reset to 1111 1111

* note that frame n+4 is equivalent to frame n of the next cycle.

Figure 7a - D-Channel 16 kb/s Operation

FP

C4i

C2

DSTo/

DSTi

IRQ

D0

D1

tif =500 nsec max

8 kb/s operation

16 kb/s operation

Microport Read/Write Access

Figure 7b - IRQ Timing Diagram

tir =500 nsec max

Rpullup= 10 k

Reset coincident with

Read/Write of Address 04 Hex

or next FP, whichever occurs first

IRQ

FP

Di-bit Group

Receive

D-Channel

Microport Read/Write Access

n-7 n-6 n-5 n-4 n-3 n-2 n-1

n

n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8

I

II III IV

D0 D1 D2 D3

No preset value

V VI VII VIII

D4 D5 D6 D7

Di-bit Group I

II III IV

V VI

Transmit D0 D1 D2 D3 D4 D5

D-Channel

Power-up reset to 1111 1111

VII VIII

D6 D7

D-Channel

Figure 7c - D-Channel 8 kb/s Operation

87

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