MT9162AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT9162AN1 Datasheet PDF : 22 Pages
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MT9162
Data Sheet
Code
+ Full Scale
+ Zero
-Zero
(quiet code)
- Full Scale
ITU-T (G.711)
µ -Law
A-Law
1000 0000
1111 1111
0111 1111
1010 1010
1101 0101
0101 0101
0000 0000
0010 1010
Table 1 - Law Selection
Analog Interfaces
Standard interfaces are provided by the MT9162. These are:
• The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 3.667Vpp µ−law and across
AIN+/AIN- 3.8Vpp A-law.
• The analog outputs (receiver), pins AOUT+/AOUT-. This internally compensated fully differential output driver is
capable of driving a load of 20k ohms.
PCM Serial Interface
A serial link is required to transport data between the MT9162 and an external digital transmission device. The
MT9162 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI).
The required mode of operation is selected via the CSL2-0 control pins. See Table 2 for selections based in CSL2-
0 pin settings.
Quiet Code
The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute
pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the
CSL2 CSL1 CSL0
External
Clock Bit
Rate (kHz)
CLOCKin
(kHz)
1
0
0
128
4096
1
0
1
256
4096
0
0
0
512
512
0
0
1
1536
1536
0
1
0
2048
2048
0
1
1
4096
4096
Figure 2 - Table 2: Bit Clock Rate Selection
TxMute pin is high. When either of these pins are low their respective paths function normally. The -Zero entry of
Table 1 is used for the quiet code definition.
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Zarlink Semiconductor Inc.
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