MT9162AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9162AN1

ISO2-CMOS 5 Volt Single Rail Codec

Zarlink Semiconductor Inc 

MT9162

Data Sheet

SSI Mode

The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input

signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if

the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.

In SSI mode the MT9162 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel

data are always in the channel defined by the STB input.

The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This

is an active high signal with an 8 kHz repetition rate.

SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is

512 kHz or greater then it is used directly by the internal MT9162 functions allowing synchronous operation. If the

available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal

MT9162 functions.

Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT9162 will re-align its

internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2,

CSL1 and CSL0 are used to program the bit rates.

Serial Port

PCM

Din

Decoder

2.05 dB

Filter/Codec and Analog Interface

Receive

Filter Gain

0 dB

-2.05 dB

Receiver

Driver

Aout +

Aout-

20kΩ

PCM

Dout

Encoder

-2.05 dB

TTrraanssmmititFiFltielrter

GGaainin

0 to0d+B7 dB

(1 dB steps)

Transmit Gain

-0.37 dB

Transmit

Gain

8.42 dB

AIN+ Analog

Input

AIN-

Internal To Device

External To Device

Figure 3 - Audio Gain Partitioning

For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the

STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.

Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during

the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation.

5

Zarlink Semiconductor Inc.

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