MT9171AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
부품명
상세내역
제조사
MT9171AN1 Datasheet PDF : 28 Pages
| |||
MT9171/72
Data Sheet
with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop
reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted.
The MT9171/72 is fabricated in Zarlink’s ISO2-CMOS process.
LOUT 1
VBias 2
VRef 3
MS2 4
MS1 5
MS0 6
RegC 7
F0/CLD 8
CDSTi/CDi 9
CDSTo/CDo 10
VSS 11
22 VDD
21 LIN
20 TEST
19 LOUT DIS
18 Precan
17 OSC1
16 OSC2
15 C4/TCK
14 F0o/RCK
13 DSTi/Di
12 DSTo/Do
MS2 5
NC 6
MS1 7
MS0 8
RegC 9
F0/CLD 10
NC 11
•
25 NC
24 LOUT DIS
23 Precan
22 OSC1
21 OSC2
20 NC
19 C4/TCK
22 PIN PDIP
LOUT
VBias
VRef
MS2
MS1
MS0
RegC
NC
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
24 PIN SSOP
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
NC
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
22 24 28
Name
Description
11
22
33
4,5, 4,5,
66
77
2
LOUT Line Out. Transmit Signal output (Analog). Referenced to VBias.
3
VBias Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD.
4
VRef Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to
VDD.
5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the
8
various operating modes for a particular application. See Table 1 for the
operating modes.
9
RegC Regulator Control output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
8 9 10 F0/CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative
pulse input for the MASTER indicating the start of the active channel times of the
device. Output for the SLAVE indicating the start of the active channel times of
the device. Output in MOD mode providing a pulse indicating the start of the C-
channel.
2
Zarlink Semiconductor Inc.
Share Link: 