MT9173AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT9173AN1
Zarlink Semiconductor Inc
MT9173AN1 Datasheet PDF : 28 Pages
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MT9173/74
Data Sheet
Pin Description (continued)
Pin #
24 28
Name
Description
14 16 DSTi/Di Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN mode.
In MOD mode this is a continuous bit stream at the bit rate selected.
15 17 F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.
16 19 C4/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.
17 21 OSC2 Oscillator Output. CMOS Output.
19 22
OSC1 Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.
20 23 Precan Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the
precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’,
the LOUT to the precanceller path is enabled and functions normally. An internal
pulldown (50 kΩ) is provided on this pin.
18 1,6,
18,
20,
25
NC No Connection. Leave open circuit
21 24 LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When
logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this pin.
22 26
TEST Test Pin. Connect to VSS.
23 27
LIN Receive Signal input (Analog).
24 28
VDD Positive Power Supply (+5 V) input.
F0
C4
DSTi
B17
B16
B15
B14
B13
B12
B11
B10
B17
DSTo
B17
B16
B15
B14
B13
B12
B11
B10
B17
F0o
Channel Time 0
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)
3
Zarlink Semiconductor Inc.
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