MT90826AL 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT90826AL Datasheet PDF : 46 Pages
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MT90826
Data Sheet
Pin Description
Pin # MQFP Pin # PBGA
12,22,33,54, D5,D6,D7,D8,D9,
66,77,90,101, E4,E10,F4,
112,125,136, F10,G4,G10,
147,157
H4,J4,J10,K5,
K6,K7
11,21,32,45,
53,60,65,71,
76,84,89,95,
100,106,111,
117,124,130,
135,141,146,
156
D4,D10,E5,E6,
E7,E8,E9,F5,
F9,G5,G9,H5,
H9,H10,J5,J6,
J7,J8,J9,K4
34
N11
Pin # LBGA
D5,D6,D7,E9,
F4,F9,G4,H4,
J6,J7,J8
D4,D9,E5,E6,
E7,E8,F5,F6,
F7,F8,G5,G6,
G7,G8,H5,H6,
H7,H8,J4
M10
35
M11
M11
36
N12
L11
37
N13
L10
38
M12
M12
42
L11
K11
43
M13
K10
Name
VDD
Description
+3.3 Volt Power Supply.
Vss
Ground.
TMS
TDI
TDO
TCK
TRST
IC1
RESET
Test Mode Select (3.3 V Input with
Internal pull-up). JTAG signal that
controls the state transitions of the TAP
controller. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data In (3.3 V Input with
Internal pull-up). JTAG serial test
instructions and data are shifted in on
this pin. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data Out (3.3 V Output).
JTAG serial data is output on this pin
on the falling edge of TCK. This pin is
held in high impedance state when
JTAG scan is not enabled.
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test
logic.
Test Reset (3.3 V Input with internal
pull-up). Asynchronously initializes the
JTAG TAP controller by putting it in the
Test-Logic-Reset state. This pin is
pulled by an internal pull-up when not
driven. This pin should be pulsed low
on power-up, or held low, to ensure that
the device is in the normal functional
mode.
Internal Connection 1 (3.3 V Input
with internal pull-down). Connect to
VSS for normal operation.
Device Reset (5 V Tolerant Input).
This input (active LOW) puts the device
in its reset state which clears the
device internal counters and registers.
10
Zarlink Semiconductor Inc.
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