MT90826AL 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT90826AL

Quad Digital Switch

Zarlink Semiconductor Inc 

MT90826

Data Sheet

Pin Description (continued)

Pin # MQFP

44

Pin # PBGA

L12

46

L13

47

K12

50

K10

51

K9

52

K13

55

J13

56

57

58

59

67-70

78,79

82,83

91-94

102-105

113-116

126-129

137-140

61-64

72-75

85-88

96-99

107-110

118,119

122,123

131-134

142-145

H13

H12

G13

G12

F13,F12,E13,E12

B13,A13

A12,B12

C11,C10,C9,C8

A7,B7,A6,B6

A5,B5,A4,B4

A2,B2,A1,B1

E2,F2,E1,F1

G11,F11,E11,D11

D13,C13,D12,C12

A11,B11,A10,B10

B9,A9,B8,A8

C7,C6,C5,C4

A3,B3

D3,C3

D2,C2,C1,D1

G1,G2,H1,H2

Pin # LBGA

L12

K12

J11

H9

G9

J12

H10

H11

H12

G12

G11

F11,F12,E12,E11

B12,A12

B11,A11

C10,C9,C8,D8

A6,A5,B6,B5,

A4,A3,B4,B3

D2,C2,C1,D1

E2,E1,F1,F2

G10,F10,D10,E10

D12,C12,D11,C11

B10,A10,B9,A9

B8,A8,A7,B7

C7,C6,C5,C4

A2,B2

B1,A1

C3,D3,E4,E3

F3,G3,G1,G2

Name

Description

IC2

Internal Connection 2 (3.3 V Input

with internal pull-down). Connect to

VSS for normal operation.

IC3

Internal Connection 3 (3.3 V Input

with internal pull-down). Connect to

VSS for normal operation.

F0i

Master Frame Pulse (5 V Tolerant

Input). This input accepts a 122 ns or

60 ns wide negative frame pulse. The

CPLL bit in the control register

determines the usage of the frame

pulse width. See Table 6 for details.

PLLGND Phase Lock Loop Ground.

PLLVDD

Phase Lock Loop Power Supply.

3.3 V

CLK

Master Clock (5 V Tolerant Input).

Serial clock for shifting data in/out on

the serial streams. This pin accepts a

clock frequency of 8.192 MHz or

16.384 MHz. The CPLL bit in the

control register determines the usage

of the clock frequency. See Table 6 for

details.

ODE

Output Drive Enable (5 V Tolerant

Input). This is the output-enable

control pin for the STo0 to STo31 serial

outputs. See Table 2 for details.

STi0/FEi0, Serial Input Streams 0 to 31 and

STi1/FEi1 Frame Evaluation Inputs 0 to 31 (5 V

STi2/FEi2 Tolerant Inputs). Serial data input

STi3/FEi3 streams. These streams may have

STi4-7/FEi4-7 data rates of 2.048, 4.096, 8.192 or

STi8-9/FEi8-9 16.384 Mbps, depending upon the

STi10-11/FEi10-11

STi12-15/FEi12-15

STi16-19/FEi16-19

value programmed at bits DR0 - DR2 in

the control register. In the frame

STi20-23/FEi20-23 evaluation mode, they are used as the

STi24-27/FEi24-27 frame evaluation inputs.

STi28-31/FEi28-31

STo0 - 3

STo4 - 7

STo8 - 11

STo12 - 15

STo16 - 19

STo20, STo21

STo22, STo23

STo24 - 27

STo28 - 31

ST-BUS Output 0 to 31 (Three-state

Outputs). Serial data output streams.

These streams may have data rates of

2.048, 4.096, 8.192, or 16.384 Mbps,

depending upon the value programmed

at bits DR0 - DR2 in the control

register.

11

Zarlink Semiconductor Inc.

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