MT90866 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT90866
Zarlink Semiconductor Inc
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
Pin Description
PBGA
Ball Number
D5, D7, D9, D11,
D12, D14, D16,
E4, E17, G4, G17,
J4, J17, K4, L17,
M4, M17, P4,
P17, T4, T17,U5,
U7, U9, U10, U12,
U14, U16
A2,A9,B2,H1
B3, B14,C3, C9,
C14, C18, C19,
C20, D4, D6, D8,
D10, D13, D15,
D17, D18, F4,
F8-F13, F17,
G7-G14, H2, H3,
H4, H6-H15, H17,
J6-J15,
K6-K15, K17, L4,
L6-L15, M6-M15,
N4, N6-15, N17,
P7-P14, P18, R1,
R2, R3, R4,
R8-R13, R17, U4,
U6, U8, U11, U13,
U15, U17, V12,
V18, W12, W19,
W20, Y12
V13
V14
V5
G2, G3, F2, F3,
G1, F1, E1, E2,
E3, D1, D2, D3,
C1, B1, A1, C2
Name
VDD
VDD5V
VSS
APLLVDD
APLLVss
RESET
STio0-3,
STio4-7,
STio8-11,
STio12-15
+3.3 Volt Power Supply.
Description
+5.0 V/+3.3 V Power Supply. If 5 V power supply is tied to these pins,
STio0-31 pins will meet 5 V PCI requirements. If 3.3 V power supply is tied
to these pins, STio0-31 pins will meet 3.3V PCI requirements.
Ground.
+3.3 Volt Analog PLL Power Supply. No special filtering is required for this
pin.
Analog PLL Ground
Device Reset (5 V Tolerant Input). This input (active low) puts the device in
its reset state; this state clears the device’s internal counters and registers.
To ensure proper reset action, the reset pin must be low for longer than
400 ns. To ensure proper operation, a delay of 100µs must be applied before
the first microprocessor access is performed after the RESET pin is set high.
The device reset also tristates STo0-27 and STio0-31, and sets the LCSTo
and BCSTo pins. When in a RESET condition, the C8_A_io, FRAME_A_io,
C8_B_io, and FRAME_B_io signals are tri-stated.
Serial Input/Output Streams 0 - 15 (5 V Tolerant PCI I/Os). In H.110
mode, these pins accept serial TDM data streams at 8.192 Mb/s with 128
channels per stream. In the 16 Mb/s mode, these pins accept serial TDM
data streams at 16.384 Mb/s with 256 channels per stream respectively.
11
Zarlink Semiconductor Inc.
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