MT90866 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

Data Sheet

List of Figures

Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2 - 27mm x 27mm PBGA (JEDEC MO-151) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3 - CT-Bus Timing for 8 Mb/s Backplane Data Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4 - ST-Bus Timing for 16 Mb/s Backplane Data Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5 - Block Programming Data in the Connection Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6 - Backplane Control (BCSTo) Timing when the STio data rate is 8 Mb/s. . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7 - Backplane Control (BCSTo) Timing when the STio data rate is 16 Mb/s. . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8 - Local Control (LCSTo) Timing when STo0-18 are operated at 8 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9 - Local Control (LCSTo) Timing when STo0-18 are operated at 4 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10 - Local Control (LCSTo) Timing when all STo0-27 are operated at 2 Mb/s . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11 - Example of Local Control (LCSTo) Timing when the Local Streams have Different Data Rates . . . . . 31

Figure 12 - Typical Timing Control Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 13 - DPLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 14 - State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15 - Block Diagram of the PLL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16 - Skew Control Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17 - DPLL Jitter Transfer Function Diagram - wide range of frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18 - Detailed DPLL Jitter Transfer Function Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19 - Local Input Bit Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 20 - Example of Backplane Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 21 - Local Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 22 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 23 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode and

Secondary Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 24 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 25 - Reference Input Timing Diagram when the input frequency = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 26 - Reference Input Timing Diagram when the input frequency = 2.048 MHz . . . . . . . . . . . . . . . . . . . . . 71

Figure 27 - Reference Input Timing Diagram when the input frequency = 1.544 Hz . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 28 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 72

Figure 29 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 72

Figure 30 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . . 72

Figure 31 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register . . . . . . . . . . . . . . . 72

Figure 32 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register . . . . . . . . . . . . . . . 73

Figure 33 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz . . . . . . . . . . . . . . . . . . . . . . 73

Figure 34 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz . . . . . . . . . . . . . . . . . . . . . . 74

Figure 35 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 36 - C1M5o Output Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 37 - Backplane Serial Stream Timing when the Data Rate is 8 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 38 - Backplane Serial Stream Timing when the Data Rate is 16 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 39 - Local Serial Stream Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 40 - Local Serial Stream Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 41 - Local Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 42 - Backplane Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 43 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 44 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 45 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 46 - Reset Pin Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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