MT90870AG2 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT90870AG2

Flexible 12 k Digital Switch (F12kDX)

Zarlink Semiconductor Inc 

MT90870

Data Sheet

Page

75

78

79

82

82

Item

Change

Figure 20, Backplane and Local Clock

Timing Diagram for ST-BUS

Changed C8i frame boundary active edge from

falling to rising edge.

Figure 22, ST-BUS Backplane Data

Changed C8i frame boundary active edge from

Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) falling to rising edge.

Figure 23, ST-BUS Backplane Data

Timing Diagram (32 Mb/s, 16 Mb/s)

Changed C8i frame boundary active edge from

falling to rising edge.

Figure 26, ST-BUS Local Timing Diagram Changed C8i frame boundary active edge from

(16 Mb/s)

falling to rising edge.

Figure 27, ST-BUS Local Data Timing

Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)

Changed FPo and C8o to FPi and C8i respectively

and shows rising C8i frame boundary active edge.

10

Zarlink Semiconductor Inc.

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