CY7C0430V-133BGC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C0430V-133BGC

3.3V 64K x 18 Synchronous QuadPort™ Static RAM

Cypress Semiconductor 

PRELIMINARY

Port 1 Operation-Control Logic Block Diagram:

(Address Readback is independent of CEs)

R/WP1

W

R

UBP1

CE0P1

CE1P1

LBP1

OEP1

9

I/O9P1–I/O17P1

I/O0P1–I/O8P1

9

Addr.

Read

Back

Port-1

I/O

Control

CY7C0430V

MRST

16

A0P1–A15P1

CNTRDP1

MKRDP1

MKLDP1

CNTINCP1

CNTLDP1

CNTRSTP1

CLKP1

Priority

Decision

Logic

MRST

CNTINTP1

Port 1

Readback

Register

Port 1

Mask Register

Port 1

Counter/

Address

Register

Port 1

Address

Decode

LBP1

UBP1

R/WP1

CE0P1

CE1P1

OEP1

CLKP1

MRST

Port 1

Interrupt

Logic

Port 1

Port 2

Port 4

RAM

Array

Port 3

INTP1

2

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