CY7C0430V-100BGC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C0430V-100BGC Datasheet PDF : 36 Pages
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PRELIMINARY
CY7C0430V
Selection Guide
fMAX2 (MHz)
Max Access Time (ns) (Clock to Data)
Max Operating Current ICC (mA)
Max Standby Current for ISB1 (mA) (All ports TTL Level)
Max Standby Current for ISB3 (mA) (All ports CMOS Level)
CY7C0430V
-133
133
4.7
750
200
1.0
CY7C0430V
-100
100
5.0
600
150
1.0
Pin Definitions
Port 1
A0P1–A15P1
I/O0P1–I/O17P1
CLKP1
LBP1
UBP1
CE0P1,CE1P1
OEP1
R/WP1
MRST
CNTRSTP1
MKLDP1
CNTLDP1
CNTINCP1
Port 2
A0P2–A15P2
I/O0P2–I/O17P2
CLKP2
LBP2
UBP2
CE0P2,CE1P2
OEP2
R/WP2
CNTRSTP2
MKLDP2
CNTLDP2
CNTINCP2
Port 3
A0P3–A15P3
I/O0P3–I/O17P3
CLKP3
LBP3
UBP3
CE0P3,CE1P3
OEP3
R/WP3
CNTRSTP3
MKLDP3
CNTLDP3
CNTINCP3
Port 4
A0P4–A15P4
I/O0P4–I/O17P4
CLKP4
LBP4
UBP4
CE0P4,CE1P4
OEP4
R/WP4
CNTRSTP4
MKLDP4
CNTLDP4
CNTINCP4
Description
Address Input/Output.
Data Bus Input/Output.
Clock Input. This input can be free running or strobed.
Maximum clock input rate is fMAX.
Lower Byte Select Input. Asserting this signal LOW en-
ables read and write operations to the lower byte. For
read operations both the LB and OE signals must be as-
serted to drive output data on the lower byte of the data
pins.
Upper Byte Select Input. Same function as LB, but to the
upper byte.
Chip Enable Input. To select any port, both CE0 AND CE1
must be asserted to their active states (CE0 ≤ VIL and
CE1 ≥ VIH).
Output Enable Input. This signal must be asserted LOW
to enable the I/O data lines during read operations. OE
is asynchronous input.
Read/Write Enable Input. This signal is asserted LOW to
write to the dual port memory array. For read operations,
assert this pin HIGH.
Master Reset Input. This is one signal for All Ports. MRST
is an asynchronous input. Asserting MRST LOW per-
forms all of the reset functions as described in the text. A
MRST operation is required at power-up.
Counter Reset Input. Asserting this signal LOW resets
the burst address counter of its respective port to zero.
CNTRST is second to MRST in priority with respect to
counter and mask register operations.
Mask Register Load input. Asserting this signal LOW
loads the mask register with the external address avail-
able on the address lines. MKLD operation has higher
priority over CNTLD operation.
Counter Load Input. Asserting this signal LOW loads the
burst counter with the external address present on the
address pins.
Counter Increment Input. Asserting this signal LOW in-
crements the burst address counter of its respective port
on each rising edge of CLK.
5
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