CXB1596AR 데이터 시트보기 (PDF) - Sony Semiconductor

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CXB1596AR

10-bit Transceiver

Sony Semiconductor 

CXB1596AR

Description of Operation

1. Transmitter block

The input 10-bit parallel data (TX0 to TX9) is latched by the external reference clock (REFCLK), converted

from parallel to serial (Parallel to Serial CONV.), and output as serial data (SDOUT/SDOUT∗).

The TXPLL multiplies REFCLK by 10 times to generate TCLK, and then frequency-divides this by 1/10 to

generate LCLK. Parallel/serial conversion uses these TCLK and LCLK as the clocks. [See P10 "Timing Charts

1) Transmitter block".]

2. Receiver block

The RXPLL recovers RCLK from the input serial data (SDIN/SDIN∗), uses this RCLK to retime the serial data

and outputs it as RDATA. The DIV (divider) frequency-divides RCLK by 1/10 to generate FCLK, and RDATA is

converted from serial to parallel (Serial to Parallel CONV.) using these two clocks (RCLK and FCLK). At the

same time the byte synchronization signal (Comma detect word) is detected during Serial to Parallel CONV.,

and 10-bit parallel data (RX0 to RX9) and the sync signal (BYTSYNC) are output. FCLK is initialized and the

10-bit parallel data is byte synchronized using this sync signal. RBC differentially outputs the clocks (RBC1

and RBC0) obtained by 1/20 frequency-dividing TCLK for loading the 10-bit parallel data. [See P11 "Timing

Charts 2) Receiver block".]

a. Input serial data amplitude detection

The serial data input block has the amplitude detection and amplitude control circuits. When the differential

amplitude of the input signal is 100mVp-p or less, the input signal is cut and the output is fixed to high level.

All parallel output data (RX0 to RX9) are high.

b. Frequency autolock

If LCKREF∗ is set high while recovering RCLK with the RXPLL, autolock mode results. In autolock mode,

RCLK is locked to 10 times REFCLK when the input serial data is no signal, or to the clock component of

the serial data when serial data is input.

When LCKREF∗ is set low, RCLK is forcibly locked to 10 times REFCLK.

c. Byte synchronization

When BYTSYNCEN is set high, Comma data within the input serial data is detected, and the detection

signal and byte synchronized 10-bit parallel data are output. At this time RBC1 and RBC0 are also

initialized and output.

When BYTSYNCEN is set low, the 10-bit parallel data is output in the arbitrary order and the RBC1 and

RBC0 edges also rise at the arbitrary position.

d. Differential clock output (RBC1 and RBC0)

RBC1 and RBC0 output at the positive phase when byte synchronization is synchronized properly and

Comma data is detected one time or more. RBC1 and RBC0 are extended when byte synchronization is

asynchronous and Comma data is detected one time.

e. Loop back

When LBEN is set high, the serial data is looped back internally. Set LBEN low to perform transmit and

receive.

–9–

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