MV1403 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MV1403

PCM MACROCELL DEMONSTRATOR

Zarlink Semiconductor Inc 

MV1403

CLK

FRS

TZS

D1

Q

CLK

FRS

TZS

D1

D3N-8N

Q

d1

d1 0 0

11

0

1

1

Macrocell transmitting timeslot zero sync. word

d1

d3-d8

d1

1

d3 d4 d5 d6 d7 d8

Macrocell transmitting timeslot zero non-sync. word

Figure 3: Timeslot zero transmitter timing

CLK

1

32

64

96

128

FRS

D D5

D6

D7

D8

D1

TS16

Q

D1 D2 D3 D4 D5 D6 D7 D8

N.B. The D input is sampled on counts 24, 56, 88 etc.

Figure 4: Timeslot sixteen transmitter timing

CLK

D

Q

TXD2

B

B

B

V

TXD1

B

B

V

NOTES:

1. B is a mark, V is an HDB3 violation.

2. There is a 3 clock period delay from input (D) to output (TXD1/2)

3. This diagram assumes the last preceding violation occurred on TXD1.

4

Figure 5: HDB3 encoder timing

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