MWS5114 데이터 시트보기 (PDF) - Intersil

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MWS5114

1024-Word x 4-Bit LSI Static RAM

Intersil 

MWS5114

ADDRESS

tRC

tAA

CS

DOUT

tCO

tCX

ACTIVE

tOTD

tOHA

VALID

NOTE:

1. WE is high during the Read Cycle. Timing measurement reference level is 1.5V.

FIGURE 1. READ CYCLE TIMING WAVEFORMS

ADDRESS

tWC

tACS

CS

tWR

tAW

WE

DIN

DON’T CARE

tW

tDSU

tDH

VALID

NOTE:

1. WE is low during the Write Cycle. Timing measurement reference level is 1.5V.

FIGURE 2. WRITE CYCLE TIMING WAVEFORMS

Data Retention Specifications at TA = 0oC to +70oC; See Figure 3

TEST

CONDITIONS

PARAMETER

SYMBOL

VDR

(V)

Minimum Data Retention Voltage

VDR

-

Data Retention Quiescent

MWS5114-3

IDD

2

Current

MWS5114-2

2

MWS5114-1

2

Chip Deselect to Data Retention Time

tCDR

-

Recovery to Normal Operation Time

tRC

-

VDD to VDR Rise and Fall Time

tR, tF

2

NOTE:

1. Typical Values are for TA = 25oC and nominal VDD.

VDD

(V)

-

-

-

-

5

5

5

LIMITS

ALL TYPES

(NOTE 1)

MIN

TYP

MAX

2

-

-

-

25

50

-

25

50

-

60

125

300

-

-

300

-

-

1

-

-

UNITS

V

µA

µA

µA

ns

ns

µs

6-165

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