25L1605 데이터 시트보기 (PDF) - Macronix International

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25L1605

16M-BIT [x 1 / x 2] CMOS SERIAL FLASH 32M-BIT [x 1 / x 2] CMOS SERIAL FLASH 64M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L1605D

MX25L3205D

MX25L6405D

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for more

details.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.

The MX25L1605D/3205D/6405D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even

after typical 100,000 program and erase cycles.

Table 1. Additional Feature Comparison

Additional

Featu-

res

Part Name

Protection and Security

Flexible

Block

protection

(BP0-BP3)

512-bit

secured OTP

Read

Performance

2 I/O Read

(50MHz)

Device ID

(command :

AB hex)

MX25L1605D

V

V

V

14 (hex)

Identifier

Device ID

(command :

90 hex)

Device ID

(command :

EF hex)

RDID

(command:

9F hex)

C2 14 (hex)

(if ADD=0)

C2 14 (hex)

(if ADD=0) C2 20 15 (hex)

MX25L3205D

V

V

C2 15 (hex) C2 15 (hex)

V

15 (hex)

(if ADD=0)

(if ADD=0) C2 20 16 (hex)

MX25L6405D

V

V

C2 16 (hex) C2 16 (hex)

V

16 (hex)

(if ADD=0)

(if ADD=0) C2 20 17 (hex)

P/N: PM1290

REV. 1.4, OCT. 01, 2008

3

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