MX29LV800CBMC-45 데이터 시트보기 (PDF) - Macronix International

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MX29LV800CBMC-45

8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY

Macronix International 

MX29LV800C T/B

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Sector Erase Set-up command and Automatic

Sector Erase command. Upon executing the Automatic

Sector Erase command, the device will automatically pro-

gram and verify the sector(s) memory for an all-zero data

pattern. The system is not required to provide any con-

trol or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when either the data on Q7 is "1" at which time the de-

vice returns to the Read mode, or the data on Q6 stops

toggling for two consecutive read cycles at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

When using the Automatic sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two "un-

lock" write cycles. These are followed by writing the

set-up command 80H. Two more "unlock" write cycles

are then followed by the sector erase command 30H.

The sector address is latched on the falling edge of WE#

or CE#, whichever happens later, while the command

(data) is latched on the rising edge of WE# or CE#,

whichever happens first. Sector addresses selected are

loaded into internal register on the sixth falling edge of

WE# or CE#, whichever happens later. Each succes-

sive sector load cycle started by the falling edge of WE#

or CE#, whichever happens later must begin within 50us

from the rising edge of the preceding WE# or CE#, which-

ever happens first. Otherwise, the loading period ends

and internal auto sector erase cycle starts. (Monitor Q3

to determine if the sector erase timer window is still open,

see section Q3, Sector Erase Timer.) Any command other

than Sector Erase (30H) or Erase Suspend (B0H) during

the time-out period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation, and

therefore will only be responded during Automatic Sector

Erase operation. When the Erase Suspend Command is

issued during the sector erase operation, the device re-

quires a maximum 20us to suspend the sector erase

operation. However, when the Erase Suspend command

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mode. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

Erase Resume, program data to , or read data from any

sector not selected for erasure.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing. The mini-

mum time from Erase Resume to next Erase Suspend

is 400us. Repeatedly suspending the device more often

may have undetermined effects.

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlock write cycles,

followed by the program set-up command. The program

address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is not

required to provide further controls or timings. The device

automatically generates the program pulses and verifies

the programmed cell margin. Table 1 shows the address

and data requirements for the byte program command

sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses

are no longer latched. The system can determine the

status of the program operation by using Q7, Q6, or RY/

P/N:PM1183

REV. 1.4, APR. 24, 2006

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