MX98715A 데이터 시트보기 (PDF) - Macronix International

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MX98715A

SINGLE CHIP FAST ETHERNET NIC CONTROLLER

Macronix International 

MX98715A

5.1.5 PCI BASE IO ADDRESS REGISTER ( PBIO ) ( Offset 13h-10h )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Configuration Base IO Address

IO/Memory Spec Indicator

bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field.

bit 7 - 1 : not used, all 0 when read

bit 31 - 8 : Defines the address assignment mapping of MX98715A CSR registers.

5.1.6 PCI Base Memory Address Register ( PBMA ) ( Offset 17h-14h )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Configuration Base Memory Address

Memory Spec Indicator

bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field.

bit 6 - 1 : not used, all 0 when read

bit 31 - 7 : Defines the address assignment mapping of MX98715A CSR registers.

5.1.7 PCI SUBSYSTEM ID REGISTER ( PSID ) ( Offset 2Ch-2Fh )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Subsystem ID (31:16)

Subsystem Vendor ID (bit 15:0)

This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. Values in

this register are loaded directly from external serial EEPROM after system reset automatically. Word location 36h of

EEPROM is subsystem vendor ID and location 35h is sub-system ID.

P/N:PM0537

REV. 1.2, FEB. 24, 1999

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